View DS1843D_4575164.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-4539; Rev 0; 5/09
Fast Sample-and-Hold Circuit
General Description
The DS1843 is a sample-and-hold circuit useful for capturing fast signals where board space is constrained. It includes a differential, high-speed switched capacitor input sample stage, offset nulling circuitry, and an output buffer. The DS1843 is optimized for use in optical line transmission (OLT) systems for burst-mode RSSI measurement in conjunction with an external sense resistor. Fast Sample Time < 300ns Hold Time > 100s Low Input Offset Buffered Output Small, 8-Pin DFN (2mm x 2mm) Pb-Free Package
Features
DS1843
Applications
Gigabit Passive Optical Network (GPON) OLT Gigabit Ethernet Passive Optical Network (GEPON) OLT GPON Optical Network Unit Sample and Hold
PART DS1843D+ DS1843D+TRL
Ordering Information
TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 8 DFN 8 DFN
+Denotes a lead(Pb)-free/RoHS-compliant package. TRL = Tape and reel.
Typical Operating Circuit
SDA DS1842/ MAX4007 3.3V VCC VINP CIN RIN CIN VINN DEN CS 3.3V SEN MON1 DS1843 VOUTP BMD MON3P MON3N CS VOUTN MON4 SCL
I2C INTERFACE VCC
MAIN MEMORY EEPROM/SRAM A/D CONFIG/RESULTS, SYSTEM STATUS BITS, ALARMS/WARNINGS, LOOKUP TABLES, USER MEMORY MOD DAC BIAS DAC
ANALOG MUX
TEMP SENSOR
12-BIT ADC
STROBE
SEN GND
CONTROL LOGIC
STROBE
CONTROLLER
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Fast Sample-and-Hold Circuit DS1843
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC .............................................-0.5V to +6V Voltage Range on VOUTP, VOUTN, VINP, VINN, SEN, DEN ............................-0.5V to (VCC + 0.5V)* *Subject to not exceeding +6V.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +125C Soldering Temperature ..............................................Refer to the IPC/JEDEC J-STD-020 Specification.
RECOMMENDED OPERATING CONDITIONS
(TA = -40C to +85C, unless otherwise noted.)
PARAMETER Supply Voltage SYMBOL VCC (Note 1) CONDITIONS MIN +2.97 TYP MAX +5.5 UNITS V
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.97V to +5.5V, TA = -40C to +85C, unless otherwise noted.)
PARAMETER Supply Current Input Capacitance Sample Capacitance Logic-Input Low Logic-Input High Input Leakage Input Voltage Output Voltage Output Impedance Output Capacitive Load Total Input Referenced Voltage Offset: Differential Total Input Referenced Voltage Offset: Single-Ended SYMBOL ICC CIN CS VIL VIH I IN VIN VOUT R OUTMAX C OUT VOS-DIFF VOS-SE (Note 1) All pins (Note 2) VINN and VINP (Note 2) SEN and DEN inputs SEN and DEN inputs VINN or VINP, SEN = 0 VIN = VINP - VINN VOUT = V OUTP - VOUTN; 100k each output pin (Note 2) Capacitance for stable operation VCC = 2.9V, 1s sample time, VIN = 6mV Voltco (VCC = 2.9V to 5.5V) VCC = 2.9V, 1s sample time, VIN = 6mV Voltco (VCC = 2.9V to 5.5V) 3.6 3.4 load on 0 0 1 0.7 x VCC 1 1.0 1.0 1.3 50 6.1 1 8 1 5 0.3 x VCC CONDITIONS MIN TYP 5.7 MAX 9 7 UNITS mA pF pF V V A V V k pF mV mV/V mV mV/V
2
_______________________________________________________________________________________
Fast Sample-and-Hold Circuit
AC ELECTRICAL CHARACTERISTICS
(VCC = +2.97V to +5.5V, TA = -40C to +85C, unless otherwise noted.) (See the Timing Diagram.)
PARAMETER Sample Time Minimum (Note 3) Delay Time Minimum Output Time Hold Time Output Step Recovery Time (Note 6) SYMBOL tS tDEL t OUT tHOLD tREC CONDITIONS VOUT is within 1% VOUT is within 35% (Note 4) Delay from SEN falling edge until valid output at VOUT to 1% accuracy (Note 5) 1V step, DEN = high 3V step, DEN = high or low t OUT MIN 300 260 10 2 100 2 3.5 TYP MAX UNITS ns ns s s s
DS1843
Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are negative. Note 2: Guaranteed by design. Note 3: VOUT at the end of the 10s hold time is within specified % of VIN during the sample window; a 2.5k resistor connected in series to both VINP and VINN (VINP - VINN = 1V). External capacitance to ground for both VINP and VINN is approximately 10pF. Note 4: The sampling capacitor must be removed from the input signal before the input signal changes. Therefore, the SEN pin must be low for a short period of time, tDEL, before the input changes. Note 5: VOUT at the end of the hold time is within 1% of VIN during the sample window (VINP - VINN = 1V). Note 6: Voltage step applied across VOUTP to VOUTN through a 5pF capacitor connected to each pin. This models the load presented by an ADC while it is sampling the DS1843's output. See the Output Buffer section. Settled within 1% of initial voltage.
Timing Diagram
VINP - VINN tS
tDEL
SEN
tOUT VOUTP - VOUTN VOLTAGE INVALID tREC tADC:ST tADC:CT EXTERNAL ADC DATA tADC:ST = EXTERNAL ADC SAMPLING TIME. tADC:CT = EXTERNAL ADC CONVERSION TIME. DEN IS CONNECTED TO VCC FOR DIFFERENTIAL OUTPUT. NOTE: THIS TIMING DIAGRAM IS APPLICABLE FOR SINGLE-ENDED AND DIFFERENTIAL OUTPUT CONFIGURATIONS.
tHOLD
DATA VALID
_______________________________________________________________________________________
3
Fast Sample-and-Hold Circuit DS1843
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
ICC vs. VCC
DS1843 toc01
ICC vs. TEMPERATURE
DS1843 toc02
ICC vs. TEMPERATURE
DEN = GND
DS1843 toc03
5.9 5.8 5.7 ICC (mA) 5.6 5.5 5.4 5.3 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 DEN = VCC DEN = GND
6.5 6.3 6.1 ICC (mA)
DEN = VCC
6.5 6.3 6.1
VCC = 5V
VCC = 5V 5.9 5.7 5.5 5.3 VCC = 3.3V
ICC (mA)
5.9 VCC = 3.3V 5.7 5.5 5.3
5.5
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
OUTPUT HOLD TIME vs. TEMPERATURE
DS1843 toc04
OUTPUT HOLD TIME vs. TEMPERATURE
DS1843 toc05
DIFFERENTIAL OUTPUT DURING SAMPLING (VINP = 6mV)
DS1843 toc06
1000 OUTPUT HOLD TIME (SECONDS)
1000 OUTPUT HOLD TIME (SECONDS)
100mV/div VOUTP 1.5V/div VSEN VOUTN
100 DEN = VCC 10
100 DEN = GND 10
VOUTP - VOUTN 5mV/div
1 -40 -15 10 35 60 85 TEMPERATURE (C)
1 -40 -15 10 35 60 85 500ns/div TEMPERATURE (C)
SINGLE-ENDED OUTPUT DURING SAMPLING (VINP = 6mV)
DS1843 toc07
DIFFERENTIAL OUTPUT, TRANSIENT WITH 10% VCC STEP (VINP = 6mV)
100mV/div VOUTP VCC = 3.3V VSEN VOUTN
DS1843 toc08
SINGLE-ENDED OUTPUT, TRANSIENT WITH 10% VCC STEP (VINP = 6mV)
VSEN 2.0V/div VCC = 3.3V
DS1843 toc09
VSEN 1.5V/div 100mV/div VOUTP ZOOMED 500ns/div VOUTP ZOOM 1V/div VCC = 3.0V
VOUTP - VOUTN 2mV/div 5mV/div
VCC = 3.0V
100mV/div
VOUTP 100s/div
20ns/div
100s/div
4
_______________________________________________________________________________________
Fast Sample-and-Hold Circuit
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
DS1843
DIFFERENTIAL OUTPUT, TRANSIENT WITH 10% VCC STEP (VINP = 1V)
VSEN 2V/div VCC = 3.3V VOUTP VCC = 3.0V 1V/div VOUTP - VOUTN VOUTN
DS1843 toc10
SINGLE-ENDED OUTPUT, TRANSIENT WITH 10% VCC STEP (VINP = 1V)
VSEN
DS1843 toc11
DIFFERENTIAL OUTPUT STEP RECOVERY, 1V OUTPUT STEP (VINP = 6mV)
DS1843 toc12
VOUTP (200mV/div) 2V/div VCC = 3.3V 200mV/div VOUTP - VOUTN VCC = 3V VOUTP 10mV/div VOUTN (200mV/div) VSEN (1V/div)
200mV/div 1V/div
100s/div
100s/div
50s/div
SINGLE-ENDED STEP RECOVERY, 1V OUTPUT STEP (VINP = 1V)
DS1843 toc13
SINGLE-ENDED OUTPUT, STEP RECOVERY, 1V OUTPUT STEP (VINP = 1V, ZOOMED IN)
DS1843 toc14
DIFFERENTIAL OUTPUT STEP RECOVERY, 1V OUTPUT STEP (VINP = 1V)
DS1843 toc15
VOUTP (200mV/div)
VOUTP (200mV/div) VSEN (1V/div) OUTPUT STEP (200mV/div)
VSEN (1V/div)
500mV/div VOUTP 500mV/div 200mV/div
VOUTN (200mV/div) VOUTP - VOUTN
VOUTP STEP (200mV/div)
50s/div
50ns/div
50s/div
DIFFERENTIAL OUTPUT STEP RECOVERY, 1V OUTPUT STEP (VINP = 1V, ZOOMED IN)
DS1843 toc16
200mV/div
VOUTP VOUTN (200mV/div) VOUTP - VOUTN (200mV/div)
50ns/div
_______________________________________________________________________________________
5
Fast Sample-and-Hold Circuit DS1843
Pin Description
PIN 1 2 3 4 5 6 7 8 NAME VCC VINP VINN DEN GND VOUTN VOUTP SEN Power-Supply Input Positive Voltage Input. Input to sample circuit. Negative Voltage Input. Input to sample circuit. Differential Output Enable. Connect to VCC for differential output or GND for single-ended output. Ground Terminal Sampled Voltage Negative Output. Buffered output of the hold capacitor. Keep unconnected or connect to GND for single-ended output mode. Sampled Voltage Positive Output and Single-Ended Output. Buffered output of the hold capacitor. Sample Enable. Enables input sampling. This input is pulsed. FUNCTION
Block Diagram
VCC VINP CIN
DS1843
VOUTN CS CS VOUTP DEN
also have parasitic capacitance (CIN). These capacitors must fully charge before SEN is switched to low in order to ensure accurate sampling. An RC time constant is created by the resistance of the voltage source connected to the DS1843's input and the capacitances on this node. See the Applications Information section for details.
Output Buffer
After sampling is complete, the sampling capacitor is switched to the output buffer. This buffer requires a small amount of time to settle, tOUT. When an ADC is used to measure the DS1843's output, a step occurs at the ADC's input caused by the ADC's internal sampling capacitor. The DS1843's recovery time, tREC, is dependent on the size of the ADC's sampling capacitor and the voltage applied across the ADC. To maximize accuracy, the ADC's sampling speed (ADC clock frequency) should be reduced until the ADC's conversion window (tADC:ST, as shown in the Timing Diagram) is larger than the DS1843's recovery time. Refer to the ADC's documentation for tADC:ST.
CIN VINN CONTROL LOGIC
SEN GND
Detailed Description
The DS1843 consists of a fully differential sampling capacitor, switches, and a differential output buffer. It is designed to operate in fiber optic burst-mode systems; however, it can be used in other applications requiring a fast sample-and-hold circuit. The output can be configured for single-ended operations.
Sampling Time and Output Error
As the sampling time (tS) is decreased, the output error increases. The output error is largely dependent on the settling time of the sampling capacitor and, to a lesser degree, the output buffer's gain error and offset voltage. Settling time can be reduced by driving the DS1843 with a lower impedance. In a typical fiber optic application, a current is applied across a 5k resistor. By using a stronger current source, the resistance and the settling time can be reduced (see the Applications Information section for details).
Input Sampling Capacitor
The input voltage is sampled using a 5pF capacitor on the positive input and another on the negative input. The capacitors are connected to the input when SEN is high. In addition to the sampling capacitors, the inputs
6
_______________________________________________________________________________________
Fast Sample-and-Hold Circuit DS1843
CURRENT MIRROR OUTPUT VINP CPAR CIN RIN VINN CIN RSW RSW
DS1843
INPUT MODEL
CS CS
Figure 1. Input Impedances for Settling Time Calculations Diagram
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS1843, decouple the power-supply pin, VCC, with a 0.01F or 0.1F capacitor. Use a high-quality X7R or equivalent ceramic surface-mount capacitor.
Figure 1 shows the simplified diagram of input impedances for settling time calculations. Sample time is divided into two parts: 1) tIST: Internal settling time (max 250ns). During this time, voltage VIN (VINP - VINN) rises with a time constant of: RIN x (CIN + CPAR) 2) tRC: During this period two things happen: a. Input VIN keeps increasing from its value at tIST to its final value with a new time constant of:
2 2 RIN x ( C IN + C PAR ) + ( R SW x C S )
DS1843 Estimated Settling Time
The settling time is dependent on the gain ratio of the current mirror used at the input of the DS1843. For example, the MAX4007 includes a 10:1 ratio current mirror. This requires a 5k resistor to create a 1V fullscale output with 2mA current input to the MAX4007. This resistor can be decreased to 2.5k by using the DS1842, which has a 5:1 ratio current mirror. Variable Definitions: RIN: Input resistor. The current mirror creates a voltage across this resistor. RSW: Resistance of series switch that connects internal circuitry to input pins after tIST time. CIN: 7pF parasitic (ESD) capacitor. CPAR: External parasitic capacitance. A current mirror's output and typical trace capacitance are less than 10pF. CS: 5pF sample capacitor. tIST: Internal settling time based on tS from the AC electrical specification. The minimum tS includes one time constant. tIST removes this time constant. tRC: RC settling time of the input.
(
)
b. RSW and CS track this VIN (input) with a time constant of RSW x CS, which is 12.5ns (worst case). Example: Approximate accuracy calculations can be done for an input voltage based on the above impedance values. These calculations can be divided into three parts. 1) Accuracy of input at tIST (250ns): Accuracy = 1 - e
RIN x ( C IN + C PAR ) - t1
where t1 = tIST = 250ns. At tIST the internal circuit tags input impedance. This causes charge redistribution to occur, which causes a dip in the input voltage. The worst-case value of the input voltage at tIST is:
VIN @ t IST
- t IST CS RIN x ( C IN + C PAR ) = 1 - x 1 - e ( CIN + C PAR + C S )
x VIN
_______________________________________________________________________________________
7
Fast Sample-and-Hold Circuit DS1843
2) Accuracy of internal circuitry between tS - tIST: Accuracy = 1 - e
-t 2 (R SW x C S ) TOP VIEW +
VCC VINP VINN DEN
Pin Configuration
where t2 = (tS - tIST) and (RSW x CS) ~ = 12ns. 3) Total accuracy of input at sampling time, tS:
-t 2 Accuracy = 1 - 1 - VIN @ t IST x e newRC
1 2
8 7 DS1843 6 5 DFN (2mm x 2mm)
SEN VOUTP VOUTN GND
(
)
-t 2 x 1 - e ( R SW x C S )
3 4
where newRC =
2 2 RIN x ( C IN + C PAR ) + ( R SW x C S )
(
)
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 8 DFN PACKAGE CODE L822+1 DOCUMENT NO. 21-0164
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

▲Up To Search▲

Price & Availability of DS1843D

	To Download DS1843D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .